A Novel Low Power Energy Recovery Full Adder Cell
نویسندگان
چکیده
A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder are then compared against three low power full adders; the transmission function adder (TFA), the dual value logic (DVL) adder and the fourteen transistor (14T) full adder. The proposed SERF adder design was proven to be superior to the other three designs in power dissipation and area, and second in propagation delay only to the DVL adder. The combination of low power and low transistor count makes the new SERF cell a viable option for low power design.
منابع مشابه
A Low Power Full Adder Cell based on Carbon Nanotube FET for Arithmetic Units
In this paper, a full adder cell based on majority function using Carbon-Nanotube Field-Effect Transistor (CNFET) technology is presented. CNFETs possess considerable features that lead to their wide usage in digital circuits design. For the design of the cell input capacitors and inverters are used. These kinds of design method cause a high degree of regularity and simplicity. The proposed des...
متن کاملSymmetrical, Low-Power, and High-Speed 1-Bit Full Adder Cells Using 32nm Carbon Nanotube Field-effect Transistors Technology (TECHNICAL NOTE)
Carbon nanotube field-effect transistors (CNFETs) are a promising candidate to replace conventional metal oxide field-effect transistors (MOSFETs) in the time to come. They have considerable characteristics such as low power consumption and high switching speed. Full adder cell is the main part of the most digital systems as it is building block of subtracter, multiplier, compressor, and other ...
متن کاملPSPICE Implementation of an 8-bit Low Power Energy Recovery Full Adder
Energy recovery technique has attracted interest of low power VLSI designers in recent years. This low power design technique has been proposed and discussed by many researchers. In this paper, we implemented energy recovery technique in the PSPICE using an 8-bit full adder circuit as an example. Full adder circuit has been widely used in arithmetic operations for addition, multipliers and Arit...
متن کاملPower Efficient adder Cell For Low Power Bio MedicalDevices
In this paper a new design of full adder cell based on Sense Energy Recovery concept using novel exclusive NOR gates is presented. Low-power consumption and delay are targeted in implementation of our design. The circuit designed is optimized for low power at 0.18-μm and 0.09 μm CMOS process technologies in full custom environment. The new circuit has been compared to the existing work based on...
متن کاملLow Power Full Adder Circuit Design Using Two Phase Adiabatic Static CMOS Logic
Adiabatic logic is used to minimize the energy loss during operation of the circuit. Using two-phase adiabatic static CMOS logic (2PASCL) the power consumption can be reduced. This paper compares the power consumption of Static Energy Recovery Full Adder(SERF) and the proposed full adder using two phase adiabatic static CMOS logic(2PASCL). The average power consumption of proposed full adder is...
متن کامل